Low Power Sram Cell of Leakage Current and Leakage Power Reduction K.venugopal P.sireesh Babu
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چکیده
A SRAM cell must meet requirements for operation in submicron. As the density of SRAM increases, the leakage power has become a significant component in chip design. The power Consumption is a major issue of today's CMOS Technology. Leakage power is major issue for short channel devices. As the technology is shrinking the leakage current is increasing very fast. so, several methods and techniques have been proposed for leakage reduction in CMOS digital integrated circuits. This paper idea of 6T, 8T and 10T models with sleep transistors. SRAM cell with sleep transistor shows better leakage reduction approach than Conventional approaches. Here in this paper Analog environment virtuoso (cadence) simulator is used for analysis of the power associated with CMOS SRAM cell for 180nm technology. Index Terms 6T Conventional SRAM cell, Leakage current and leakage power, 6T, 8T and 10T sleep transistor models, Subthreshold leakage current reduction.
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